This invention generally relates to metallic electrodeposition and more particularly to a method for integrating an electrodeposition and electro-mechanical polishing process in semiconductor manufacturing to selectively fill with metal anisotropically etched semiconductor features.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities increased device speed.
As circuit densities increase, the widths of vias, contacts, metal interconnect lines, and other features, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers, through the use low-k (low dielectric constant) materials, has remained substantially constant. Consequently, the aspect ratios for the features, i.e., their height divided by width, has increased thereby creating additional challenges in adequately filling the sub-micron features with, for example, copper metal. Many traditional deposition processes such as chemical vapor deposition (CVD) have difficulty filling increasingly high aspect ratio features, for example, where the aspect ratio exceeds 2:1, and particularly where it exceeds 4:1.
As a result of these process limitations, electroplating or electrodeposition is now a preferable method for filling metal interconnects structures such as via openings and trench line openings on semiconductor devices. Typically, electroplating uses an electrolyte including positively charged ions of deposition material, for example metal ions, in contact with a negatively charged substrate (cathode) having a source of electrons to deposit (plate out) the metal ions onto the charged substrate, for example, a semiconductor wafer. A thin metal layer (seed layer) is first deposited on the semiconductor wafer to form a liner in high aspect ratio anisotropically etched features to provide a continuous electrical path across the surfaces. An electrical current is supplied to the seed layer whereby the semiconductor wafer surface including etched features are electroplated with an appropriate metal, for example, aluminum or copper, to fill the features.
One exemplary process for forming a series of interconnected multiple layers, for example, is a damascene or dual damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a series insulating layers are deposited to include a series of interconnecting metallization structures such as vias and metal line interconnects to electrically interconnect areas within the multilayer device and contact layers to interconnect the various devices on the chip surface. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multilayer device. Metal interconnect lines typically serve to selectively interconnect conductive regions within a layer of a multilayer device. Vias and metal interconnect lines are selectively interconnected in order to form the necessary electrical connections.
In filling the via openings and trench line openings with metal, for example, copper, electroplating is a preferable method to achieve superior step coverage of sub-micron etched features. The method generally includes first depositing a barrier layer over the etched opening surfaces, such as via openings and trench line openings, depositing a metal seed layer, for example copper, over the barrier layer, and then electroplating a metal, for example copper, over the seed layer to fill the etched features to form conductive vias and trench lines. Finally, the electro deposited layer and the dielectric layers are planarized, for example, by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Metal electroplating (electrodeposition) in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on semiconductor wafers involve positioning the plating surface of the semiconductor wafer within an electrolyte solution including an anode with the electrolyte impinging perpendicularly on the plating surface. The plating surface is in electrical communication with an electrical power source thereby forming the cathode of the plating system such that ions in the plating solution deposit on the conductive portion of the plating surface, for example a semiconductor wafer surface.
More recent electroplating processes use self contained assemblies where the anode and semiconductor wafer are in close proximity to carry out both electroplating and electropolishing. Typically the semiconductor wafer surface is spaced apart from the anode in the electroplating solution during electrodeposition and contacts the anode during the electropolishing process where the semiconductor wafer becomes the anode and the anode assembly acts as a cathode.
A recurring problem in copper electrodeposition process is that excess copper must be deposited on the wafer process surface during electrodeposition which conformally deposits metal to fill anisotropically etched semiconductor features. The excess copper is necessary to allow for adequate planarization to be achieved in a subsequent chemical mechanical polishing (CMP) process to prepare the wafer for manufacturing subsequent semiconductor device levels. Typically, the excess copper layer is removed following electrodeposition according to chemical mechanical polishing (CMP) which generally includes an abrasive polishing solution and a polishing pad applied with a significant downforce to the semiconductor wafer surface. The copper layer is typically deposited over an insulating dielectric layer in which the semiconductor features are anisotropically etched. With the increasing use of low dielectric constant materials (e.g.,  less than 3.5) which typically have a lower strength and poor adhesion to copper due to, among other reasons, an increased level of porosity, copper CMP may cause peeling of the electrodeposited copper layer thereby reducing manufacturing yield. In addition, the copper CMP process increases a throughput time and involves the use of costly CMP apparatus and polishing chemicals. Moreover, the copper CMP process may induce other wafer defects including preferential polishing of copper semiconductor features referred to as dishing and erosion.
One approach to reduce the necessity of lengthened copper CMP polishing times has been to electropolish the semiconductor wafer following an electrodeposition process to reduce the thickness of the excess copper layer. This approach creates the difficulty that electropolishing which conformally removes the excess copper does not achieve the desired degree of planarization necessary for subsequent processing steps.
These and other shortcomings demonstrate a need in the semiconductor processing art to develop a method for electrodeposition whereby the necessity for a subsequent CMP planarization step is avoided to increase a semiconductor wafer throughput and yield.
It is therefore an object of the invention to provide a method for electrodeposition whereby the necessity for a subsequent CMP planarization step is avoided to increase a semiconductor wafer throughput and yield while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal.
In a first embodiment, the method includes a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.